Version 1.2 (R14SP1) Link for ModelSim® Release Notes

Version 1.2 (R14SP1) Link for ModelSim

This table summarizes what's new in V1.2 (R14SP1):

New features and changes introduced in this version are:

• VHDL Cosimulation Block Enhancements

• Support for MATLAB/ModelSim Sessions Between Platforms of Differing Byte Ordering

VHDL Cosimulation Block Enhancements

We have made major enhancements and revisions to the functionality and the appearance of the VHDL Cosimulation block. This release note summarizes these changes.

Per-Port Sample Time Specification for Outputs Supported

You can now specify an independent sample time for each output port on a VHDL Cosimulation block. Using the Ports pane of the VHDL Cosimulation block parameters dialog (see Ports Pane) you can specify an explicit sample time, or specify a default (-1). In the default case, Simulink sets the sample time to the fastest sample time used in the block.

Per-Port Data Type Specification for Outputs Supported

You can now force fixed point data types on individual output ports of a VHDL Cosimulation block, using the Ports pane of the VHDL Cosimulation block parameters dialog (see Ports Pane). By default, Simulink determines the data type by back-propagation or by querying ModelSim. Alternatively, you can assign an explicit data type (with optional fraction length) using the Data Type and Fraction length fields.

Specification of Independent Clock Sample Times Supported

Using the Clocks pane of the VHDL Cosimulation block parameters dialog (see Clocks Pane). you can now specify period of each clock in the model explicitly, or specify -1 to use a default value supplied by Simulink. In the default case, Simulink sets the clock period to the fastest sample time used in the block.

Improved and Revised VHDL Cosimulation Block Parameters Dialog Box

The sections below illustrate and summarize the improvements that have been made to the VHDL Cosimulation block GUI.

Ports Pane.   The figure below shows the revised layout of the Ports pane of the VHDL Cosimulation Block Parameters dialog box.

The Ports pane now displays a scrolling list of VHDL signals corresponding to ports on the VHDL Cosimulation block. The buttons to the right of the list let you add, delete, or reposition signals in the list. To set the properties of a signal, select the desired signal from the list and enter values into the property fields below the list.

The Ports pane supports the following properties and capabilities:

• The Full HDL Name field lets you enter the VHDL pathname for a signal anywhere in the hierarchy of the VHDL model.

• The I/O Mode menu lets you select whether a signal is associated with an input or output port.

• The Sample Time field lets you specify a sample time, per port, for outputs.

• The Data Type and Fraction length fields let you specify a fixed point data type for individual output ports of a VHDL Cosimulation block.

Connection Pane.   The figure below shows the default layout of the Connection pane (formerly labelled as the Comm pane) of the VHDL Cosimulation Block Parameters dialog box.

By default, the block is configured for shared memory communication. If you select TCP/IP socket mode communication, the pane displays additional properties, as shown in the figure below.

When the new Show connection info on icon option is selected, information about the selected communication method and (if applicable) communication options is displayed on the VHDL Cosimulation block icon in the Simulink model.

Clocks Pane.   The figure below shows the default layout of the Clocks pane of the VHDL Cosimulation Block Parameters dialog box.

The Clocks pane now displays a scrolling list of VHDL clock signals The buttons to the right of the list let you add, delete, or reposition clock signals in the list. To set the properties of a clock signal, select the desired signal from the list and enter values into the property fields below the list.

The Clocks pane supports the following properties and capabilities:

• The Full HDL Name field lets you enter the VHDL pathname for a clock signal.

• The Edge menu lets you specify either a rising-edge clock or a falling-edge clock.

• The Period field lets you specify the clock period explicitly, or specify -1 to use a default value supplied by Simulink.

Tcl Pane.   The figure below shows the revised layout of the Tcl pane of the VHDL Cosimulation Block Parameters dialog box.

You can now specify Tcl commands in the text boxes in one line per command format, or enter multiple commands per line by appending each command with a semicolon (;), the standard Tcl concatenation operator.

Support for MATLAB/ModelSim Sessions Between Platforms of Differing Byte Ordering

You can now run MATLAB/ModelSim sessions in TCP/IP socket mode between platforms having different byte ordering.

Compatibility Considerations

In previous releases, Link for ModelSim required that when MATLAB/ModelSim sessions were run in TCP/IP socket mode, all connected systems must support the same byte ordering (e.g., little-endian or big-endian). This restriction has been removed.

The following table illustrates the currently supported MATLAB / ModelSim connections.

Version 1.3 (R14SP1+) Link for ModelSim

Compatibility Summary for EDA Simulator Link MQ Software