EDA Simulator Link DS 2.0
for Synopsys Discovery

Product Description

• Introduction and Key Features
• Working with EDA Simulator Link DS
• Typical Applications
• Using EDA Simulator Link DS with MATLAB
• Using EDA Simulator Link DS with Simulink

Introduction

EDA Simulator Link™ DS is a cosimulation interface that provides a bidirectional link between MATLAB® and Simulink® and the Synopsys® Discovery™ VCS™ MX family of simulators. This product enables you to use MATLAB or Simulink with Synopsys Discovery for efficient verification of HDL code. It provides native cosimulation support for VHDL®, Verilog®, and mixed-language designs.

EDA Simulator Link DS enables MATLAB code or Simulink models to function as a test bench, generating stimulus for an HDL simulation and analyzing the simulation’s response. The product also lets you replace multiple HDL components with MATLAB code or Simulink models, enabling simulation of the complete system before all the HDL design elements are available.

For greater development flexibility, EDA Simulator Link DS enables interactive cosimulation on a single computer, across platforms, or across a network.

Key Features

• Full VHDL, Verilog, and mixed-language cosimulation support for MATLAB or Simulink
• Test bench capability, enabling the use of MATLAB code or Simulink models to stimulate HDL code and check its response
• Component capability, enabling simulation of MATLAB code or Simulink models in place of entities not yet coded in HDL
• Cross-platform cosimulation using MATLAB and Simulink on Windows® with Synopsys VCS on Linux®
• Single-machine, multiple-machine, and cross-network cosimulation using shared-memory and TCP/IP-socket communications modes
• Interactive or batch mode cosimulation, debugging, testing, and verification of HDL

Elaboration of a floating-point reference algorithm and verification of a Verilog implementation using a cosimulation interface. Click on image to see enlarged view.

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